In bipolar integrated circuits, chip performance depends not only on the internal circuits, but also on the peripherals or external circuits, such as drivers and receivers, which communicate to off chip circuits. However, for optimum performance, it is desirable to have the internal circuits operating at higher speeds and at higher gains than those in the peripherals.
These improvements to performance (.UPSILON..sub.e) and gain (h.sub.FE) for the internal circuits cannot be at the expense of other critical parameters for the external circuits, such as the breakdown voltage between the emitter and collector, BVCEO, current handling capabilities, etc. This would ensure faster internal circuits while maintaining the necessary package compatibility in terms of wiring rules, delay equations and noise criteria. This type of discriminatory operation of internal circuits versus external circuits has not been practical.
Among the most important parameters that affect the delay in bipolar transistors is the base profile in the intrinsic device region. The device can be made faster by decreasing the base width. This can be accomplished by either a shallow base diffusion or by a deeper emitter. However, the problem with either of the above approaches is that, in the past, it was not simple to achieve different basewidths on different areas of the chip, without resorting to a complicated sequence of heat cycles and process steps, such as described in H. C. Lin U.S. Pat. No. 3,335,341; R. J. Widlar U.S. Pat. No. 3,566,218; U. G. Baitinger et al. U.S. Pat. No. 3,810,123; N. Horie et al. U.S. Pat. No. 3,969,748; H. Mayumi et al. U.S. Pat. No. 4,045,784; or Komatsu et al. U.S. Pat. No. 4,224,088.
It is known that thin base regions are very desirable for high performance bipolar transistor devices which have very high operating speeds and amplification characteristics. There have been methods proposed for producing such very narrow base regions over the years. Of the methods that have been used, diffusion, and ion implantation with or without the combined use of etching have been used to produce narrow base region devices.
One line of patents which have worked toward the narrow base structure involves what is called the pedestal transistor. The patents required accurately controlling junction depths, epitaxial layer thicknesses, surface uniformity, and quality to form these devices of small geometry. Examples of this technology is the H. N. Yu U.S. Pat. No. 3,312,881; F. Barson et al. U.S. Pat. No. 3,489,622; K. G. Ashar U.S.Pat. No. 3,677,837 and K. G. Ashar et al. U.S. Pat. No. 3,717,515. Each of these patents attempt to control the narrow base width through various diffusion techniques and in no way utilize the etching technique of the present invention. Another series of patents and publications utilize the etching technique for removal of portions of the base region followed by the emitter diffusion. The examples of this technology is the W. Meer et al. U.S. Pat. No. 3,551,220; Hans-Martin Rein et al. U.S. Pat. No. 3,669,760; Aung San U U.S. Pat. No. 3,926,695; N. Horie U.S. Pat. No. 4,030,954 and K. Malin IBM Technical Disclosure Bulletin, Vol. 20, No. 4, September 1977, pages 1495-1496. While these publications do describe etching, they all describe a chemical etching technique which produces the undercutting of the etching mask within the base region. This chemical etching process cannot be well controlled and the etching solution introduces unwanted impurities into the small dimensioned geometries that workers in the field desire in the very large scale integration technology.
Plasma or reactive ion etching is a technique which has been developed for etching metals, semiconductor materials and dielectrics in the manufacture of integrated circuit devices. In particular, the method of reactive ion etching which is capable of doing anisotropic etching wherein very high aspect ratios is obtainable. High aspect ratio means, in this context, the ratio of vertical etching is much greater than the horizontal etching. The process involves the use of a plasma or ionized gas containing a variety of highly reactive material, such as ions, free electrons, and free radicals. The plasma used in etching may be maintained at relatively low temperatures and pressures in the range of less than about 20 Torr. The process has been used to etch depressions in silicon semiconductor bodies for a variety of reasons, such as shown in the A. K. Hochberg U.S. Pat. No. 3,966,577 issued June 29, 1976; J. A. Bondur et al. U.S Pat. No. 4,104,086 and J. A. Bondur et al. U.S. Pat. No. 4,139,442. However, there is no suggestion or understanding of the need in any of these patents of the use of the reactive ion etching technique for making very narrow base bipolar transistor structures.